1. Technical Field
The present invention relates in general to multi-layer circuits and in particular to a multi-layer circuit having decreased interlayer registration requirements and a method for fabricating the same. Still more particularly, the present invention relates to a multi-layer flexible circuit having a via matrix interlayer connection and a method for fabricating the same.
2. Description of the Related Art
A typical state-of-the-art integrated circuit chip carrier, for example, a single chip module (SCM) or multi-chip module (MCM), includes an integrated circuit chip, which is mounted on a multi-layer flexible circuit that provides interconnections between the integrated circuit chip and other circuitry, such as other integrated circuit devices mounted on a printed circuit card to which the integrated circuit chip carrier is attached. Typically, the flexible circuit within an integrated circuit chip carrier comprises a thin, electrically insulative, flexible film formed from an organic polymeric material, such as polyimide. The flexible film serves as a substrate that supports one or more integrated circuit chips, which are each electrically connected and mechanically attached to a set of contact pads on the upper surface of the flexible film by solder balls or other similar attachment means. Each contact pad on the upper surface of the flexible film is electrically connected by a metallized circuit trace to a single metallized via extending through the flexible film. The metallized vias are in turn connected on the lower surface of the flexible film to either signal traces, which conduct electrical signals to and from the integrated circuit chip, or to a copper backplane, which provides a reference (ground) voltage or electrical power to the integrated circuit chip.
In many conventional processes for fabricating a flexible circuit, the vias are formed in the substrate subsequent to the deposition of a metal layer on at least one side of the flexible film. For example, in one conventional process, a seed layer that promotes adhesion is vapor phase deposited on the upper and lower surface of the flexible film substrate. A thin copper layer is then flash plated over the seed layer. Next, the upper and lower surfaces of the substrate are each laminated with photoresist and exposed through photomasks in order to delineate circuit traces on the upper surface of the substrate and a corresponding via pattern on the lower surface of the substrate. After the photoresist is developed, the upper surface is electroplated to form the metallized circuit traces. Next, vias are chemically etched through the flexible film at the patterned locations on the lower surface. Following the formation of the vias, the photoresist is stripped from the upper and lower surfaces and the flexible film is subjected to a number of baking and cleaning steps to prepare the vias for subsequent processing. Care must be taken to ensure that the vias are properly cleaned prior to performing further process steps in order to avoid contamination-related problems, such as blistering. A thin seed layer is then deposited on the via sidewalls and lower surface of the substrate. Thereafter, copper is plated on the via sidewalls and lower surface to form the via metallizations and copper backplane or lower surface circuitry.
Although preforming vias in the flexible film prior to metallization would be preferable in terms of streamlining the fabrication process (e.g., by permitting simultaneous metallization of the upper and lower surfaces of the substrate) and avoiding via contamination-related problems, preforming vias in the substrate prior to metallization also presents several difficulties. In particular, the flexible film undergoes a significant amount of thermal distortion due to the high temperatures associated with the vapor phase deposition of the seed layer. Heating the flexible film to such temperature extremes causes a systematic shrinkage of the flexible film in the cross-tape (transverse) direction and elongation of the flexible film in the down-tape direction. The displacement of vias resulting from the thermal distortion of the flexible film is undesirable because the subsequent photolithographic patterning of metallized traces on the upper surface of the flexible film must account for the displacement of vias in order to obtain electrical connections between the upper surface metallized traces and the flexible film backplane or lower surface signal traces. Although to some extent, the systematic thermal displacement of vias can be compensated for in the photomask utilized to pattern the metallized traces, random displacements of vias, for which a static photomask cannot compensate, are also common. Because of the random thermal displacements of vias, flexible circuits fabricated from flexible film having preformed vias can be rendered defective.
A second related problem more generally associated with the economical fabrication of state-of-the-art flexible circuits is the interlayer registration of lands, traces, and other upper surface metallizations with metallized vias and lower surface metallizations. Because of the demand for ever increasing miniaturization, especially in constrained package applications such as hearing aids and cellular telephones, registration between the circuit metallizations and metallized vias in flexible circuits must be extremely precise. To achieve satisfactory interlayer registration, the alignment of flexible circuit features such metallized traces and metallized vias can require prohibitively expensive registration equipment employing sophisticated machine vision technology.
A third problem concomitant with the fabrication of flexible circuits is the establishment of reliable connections between flexible circuit layers through the metallized vias. When fabrication processes are employed that form, but do not fill the vias prior to performing subsequent processing steps, contaminants can be entrained within the vias during plating that can subsequently cause faulty interlayer connections. Such reliability concerns are particularly prevalent when aqueous processing methods are utilized because the surface tension of aqueous cleaning agents can inhibit the wetting of vias and other high aspect ratio circuit features. Furthermore, because connections between upper and lower surface metallizations are typically established through a single via, failure of one via interconnection, for example, between a power plane or lower surface signal trace and an upper surface metallization, can result in failure of an integrated circuit chip.
As should thus be apparent, a flexible circuit for an integrated circuit chip carrier is needed which permits the fabrication of circuit features having smaller geometries and greater densities and which decreases interlayer registration requirements. In addition, a flexible circuit interlayer connection is needed that provides improved reliability.